35986841_10216840653711318_1105697261150535680_n

Digital system test and testable design using HDL models and architectures / Zainalabedin Navabi

By: Navabi, Zainalabedin
Material type: TextTextPublisher: New York : Springer, c2011Edition: 1st edDescription: 1 online resource (xxiii, 435 p.) : illISBN: 9781441975485 (electronic bk.); 1441975489 (electronic bk.)Subject(s): Digital integrated circuits -- Testing | Digital integrated circuits -- Design and construction | Verilog (Computer hardware description language)Genre/Form: Electronic booksDDC classification: 621.3815 LOC classification: TK7874 | .N38 2011Online resources: SpringerLINK Connect to electronic resource | SpringerLINK Connect to electronic resource (off-campus access)
Contents:
Simple Sequential Testbench -- Limiting Data Sets -- Synchronized Data and Response Handling -- Random Time Intervals -- Text IO -- Simulation Code Coverage -- PLI Basics -- Access Routines -- Steps for HDL/PLI Implementation -- Fault Injection in the HDL/PLI Environment -- Summary -- References -- Fault and Defect Modeling -- Fault Modeling -- Fault Abstraction -- Functional Faults -- Structural Faults -- Structural Gate Level Faults -- Recognizing Faults -- Stuck-Open Faults -- Stuck-at-0 Faults -- Stuck-at-1 Faults -- Bridging Faults -- State-Dependent Faults -- Multiple Faults -- Single Stuck-at Structural Faults -- Detecting Single Stuck-at Faults -- Issues Related to Gate Level Faults -- Deteeting Bridging Faults -- Undetectable Faults -- Redundant Faults -- Fault Collapsing -- Indistinguishable Faults -- Equivalent Single Stuck-al Faults -- Gate-Oriented Fault Collapsing -- Line-Oriented Fault Collapsing -- Problem with Reconvergenl Fanouts -- Dominance Fault Collapsing -- Fault Collapsing in Verilog -- Verilog Testbench for Fault Collapsing -- PLI Implementation of Fault Collapsing -- Summary -- References -- Fault Simulation Applications and Methods -- Fault Simulation -- Gate-Level Fault Simulation -- Fault Simulation Requirements -- HDL Environment -- Sequential Circuit Fault Simulation -- Fault Dropping -- Related Terminologies -- Fault Simulation Applications -- Fault Coverage -- Fault Simulation in Test Generation --
Fault Dictionary Creation -- Fault Simulation Technologies -- Serial Fault Simulation -- Parallel Fault Simulation -- Concurrent Fault Simulation -- Deductive Fault Simulation -- Comparison of Deductive Fault Simulation -- Critical Path Tracing Fault Simulation -- Differential Fault Simulation -- Summary -- References -- Test Pattern Generation Methods and Algorithms -- Test Generation Basics -- Boolean Difference -- Test Generation Process -- Fault and Tests -- Terminologies and Definitions -- Controllability and Observability -- Controllability -- Observability -- Probability-Based Controllability and Observability -- SCOAP Controllability and Observability -- Distances Based -- Random Test Generation -- Limiting Number of Random Tests -- Combinational Circuit RTG -- Sequential Circuit RTG -- Summary -- References -- Deterministic Test Generation Algorithms -- Deterministic Test Generation Methods -- Two-Phase Test Generation -- Fault-Oriented TG Basics -- D-Algorithm -- PODEM (Path-Oriented Test Generation) -- Other Deterministic Fault-Oriented TG Methods -- Fault-Independent Test Generation -- Sequential Circuit Test Generation -- Test Data Compaction -- Forms of Test Compaction -- Test Compatibility -- Static Compaction -- Dynamic Compaction -- Summary -- References -- Design for Test by Means of Scan -- Making Circuits Testable -- Tradeoffs -- Testing Sequential Circuits -- Testability of Combinational Circuits -- Testability Insertion -- Improving Observability --
Improving Controllability -- Sharing Observability Pins -- Sharing Control Pins -- Reducing Select Inputs -- Simultaneous Control and Observation -- Full Scan DFTTechnique -- Full Scan Insertion -- Flip-Flop Structures -- Full Scan Design and Test -- Scan Architectures -- Full Scan Design -- Shadow Register DFT -- Partial Scan Methods -- Multiple Scan Design -- Other Scan Designs -- RT Level Scan Design -- RTL Design Full Scan -- RTL Design Multiple Scan -- Scan Designs for RTL -- Summary -- References -- Standard IEEE Test Access Methods -- Boundary Scan Basics -- Boundary Scan Architecture -- Test Access Port -- Boundary Scan Registers -- TAP Controller -- Decoder Unit -- Select and Other Units -- Boundary Scan Test Instructions -- Mandatory Instructions -- Board Level Scan Chain Structure -- One Serial Scan Chain -- Multiple-Scan Chain with One Control Test Port -- Multiple-Scan Chains with One TDI, TDO but Multiple TMS -- Multiple-Scan Chain, Multiple Access Port -- RT Level Boundary Scan -- Inserting Boundary Scan Test Hardware for CUT -- Two Module Test Case -- Virtual Boundary Scan Tester -- Boundary Scan Description Language -- Summary -- References -- Logic Built-in Self-test -- BIST Basics -- Memory-based BIST -- BIST Effectiveness -- BISTTypes -- Designing a BIST -- Test Pattern Generation -- Engaging TPGs -- Exhaustive Counters -- Ring Counters -- Twisted Ring Counter -- Linear Feedback Shift Register --
Output Response Analysis -- Engaging ORAs -- One's Counter -- Transition Counter -- Parity Checking -- Serial LFSRs (SISR) -- Parallel Signature Analysis -- BIST Architectures -- BTST-related Terminologies -- Centralized and Separate Board-level BIST Architecture (CSBL) -- Built-in Evaluation and Self-test (BEST) -- Random Test Socket (RTS) -- LSSD On-chip Self Test -- Self-testing Using MTSR and SRSG -- Concurrent BIST -- BILBO -- Enhancing Coverage -- RT Level BIST Design -- CUT Design, Simulation, and Synthesis -- RTS BIST Insertion -- Configuring the RTS BIST -- Incorporating Configurations in BIST -- Design of STUMPS -- RTS and STUMPS Results -- Summary -- References -- Test Compression -- Test Data Compression -- Compression Methods -- Code-based Schemes -- Scan-based Schemes -- Decompression Methods -- Decompression Unit Architecture -- Cyclical Scan Chain -- Code-based Decompression -- Scan-based Decompression -- Summary -- References -- Memory Testing by Means of Memory BIST -- Memory Testing -- Memory Structure -- Memory Fault Model -- Stuck-At Faults -- Transition Faults -- Coupling Faults -- Bridging and State CFs -- Functional Test Procedures -- March Test Algorithms -- March C-Algorithm -- MATS+Algorithm -- Other March Tests -- MBIST Methods -- Simple March MBIST -- March C- MBIST -- Disturb MBIST -- Summary -- References
In: SpringerLink
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Books Books Centeral Library
Second Floor - Engineering & Architecture
621.3815 N.Z.D 2011 (Browse shelf) Available 24048

Includes bibliographical references and index

Note continued: 2.8.3. Simple Sequential Testbench -- 2.8.4. Limiting Data Sets -- 2.8.5. Synchronized Data and Response Handling -- 2.8.6. Random Time Intervals -- 2.8.7. Text IO -- 2.8.8. Simulation Code Coverage -- 2.9. PLI Basics -- 2.9.1. Access Routines -- 2.9.2. Steps for HDL/PLI Implementation -- 2.9.3. Fault Injection in the HDL/PLI Environment -- 2.10. Summary -- References -- 3. Fault and Defect Modeling -- 3.1. Fault Modeling -- 3.1.1. Fault Abstraction -- 3.1.2. Functional Faults -- 3.1.3. Structural Faults -- 3.2. Structural Gate Level Faults -- 3.2.1. Recognizing Faults -- 3.2.2. Stuck-Open Faults -- 3.2.3. Stuck-at-0 Faults -- 3.2.4. Stuck-at-1 Faults -- 3.2.5. Bridging Faults -- 3.2.6. State-Dependent Faults -- 3.2.7. Multiple Faults -- 3.2.8. Single Stuck-at Structural Faults -- 3.2.9. Detecting Single Stuck-at Faults -- 3.3. Issues Related to Gate Level Faults -- 3.3.1. Deteeting Bridging Faults -- 3.3.2. Undetectable Faults -- 3.3.3. Redundant Faults -- 3.4. Fault Collapsing -- 3.4.1. Indistinguishable Faults -- 3.4.2. Equivalent Single Stuck-al Faults -- 3.4.3. Gate-Oriented Fault Collapsing -- 3.4.4. Line-Oriented Fault Collapsing -- 3.4.5. Problem with Reconvergenl Fanouts -- 3.4.6. Dominance Fault Collapsing -- 3.5. Fault Collapsing in Verilog -- 3.5.1. Verilog Testbench for Fault Collapsing -- 3.5.2. PLI Implementation of Fault Collapsing -- 3.6. Summary -- References -- 4. Fault Simulation Applications and Methods -- 4.1. Fault Simulation -- 4.1.1. Gate-Level Fault Simulation -- 4.1.2. Fault Simulation Requirements -- 4.1.3. HDL Environment -- 4.1.4. Sequential Circuit Fault Simulation -- 4.1.5. Fault Dropping -- 4.1.6. Related Terminologies -- 4.2. Fault Simulation Applications -- 4.2.1. Fault Coverage -- 4.2.2. Fault Simulation in Test Generation --

Note continued: 4.2.3. Fault Dictionary Creation -- 4.3. Fault Simulation Technologies -- 4.3.1. Serial Fault Simulation -- 4.3.2. Parallel Fault Simulation -- 4.3.3. Concurrent Fault Simulation -- 4.3.4. Deductive Fault Simulation -- 4.3.5. Comparison of Deductive Fault Simulation -- 4.3.6. Critical Path Tracing Fault Simulation -- 4.3.7. Differential Fault Simulation -- 4.4. Summary -- References -- 5. Test Pattern Generation Methods and Algorithms -- 5.1. Test Generation Basics -- 5.1.1. Boolean Difference -- 5.1.2. Test Generation Process -- 5.1.3. Fault and Tests -- 5.1.4. Terminologies and Definitions -- 5.2. Controllability and Observability -- 5.2.1. Controllability -- 5.2.2. Observability -- 5.2.3. Probability-Based Controllability and Observability -- 5.2.4. SCOAP Controllability and Observability -- 5.2.5. Distances Based -- 5.3. Random Test Generation -- 5.3.1. Limiting Number of Random Tests -- 5.3.2. Combinational Circuit RTG -- 5.3.3. Sequential Circuit RTG -- 5.4. Summary -- References -- 6. Deterministic Test Generation Algorithms -- 6.1. Deterministic Test Generation Methods -- 6.1.1. Two-Phase Test Generation -- 6.1.2. Fault-Oriented TG Basics -- 6.1.3. D-Algorithm -- 6.1.4. PODEM (Path-Oriented Test Generation) -- 6.1.5. Other Deterministic Fault-Oriented TG Methods -- 6.1.6. Fault-Independent Test Generation -- 6.2. Sequential Circuit Test Generation -- 6.3. Test Data Compaction -- 6.3.1. Forms of Test Compaction -- 6.3.2. Test Compatibility -- 6.3.3. Static Compaction -- 6.3.4. Dynamic Compaction -- 6.4. Summary -- References -- 7. Design for Test by Means of Scan -- 7.1. Making Circuits Testable -- 7.1.1. Tradeoffs -- 7.1.2. Testing Sequential Circuits -- 7.1.3. Testability of Combinational Circuits -- 7.2. Testability Insertion -- 7.2.1. Improving Observability --

Note continued: 7.2.2. Improving Controllability -- 7.2.3. Sharing Observability Pins -- 7.2.4. Sharing Control Pins -- 7.2.5. Reducing Select Inputs -- 7.2.6. Simultaneous Control and Observation -- 7.3. Full Scan DFTTechnique -- 7.3.1. Full Scan Insertion -- 7.3.2. Flip-Flop Structures -- 7.3.3. Full Scan Design and Test -- 7.4. Scan Architectures -- 7.4.1. Full Scan Design -- 7.4.2. Shadow Register DFT -- 7.4.3. Partial Scan Methods -- 7.4.4. Multiple Scan Design -- 7.4.5. Other Scan Designs -- 7.5. RT Level Scan Design -- 7.5.1. RTL Design Full Scan -- 7.5.2. RTL Design Multiple Scan -- 7.5.3. Scan Designs for RTL -- 7.6. Summary -- References -- 8. Standard IEEE Test Access Methods -- 8.1. Boundary Scan Basics -- 8.2. Boundary Scan Architecture -- 8.2.1. Test Access Port -- 8.2.2. Boundary Scan Registers -- 8.2.3. TAP Controller -- 8.2.4. Decoder Unit -- 8.2.5. Select and Other Units -- 8.3. Boundary Scan Test Instructions -- 8.3.1. Mandatory Instructions -- 8.4. Board Level Scan Chain Structure -- 8.4.1. One Serial Scan Chain -- 8.4.2. Multiple-Scan Chain with One Control Test Port -- 8.4.3. Multiple-Scan Chains with One TDI, TDO but Multiple TMS -- 8.4.4. Multiple-Scan Chain, Multiple Access Port -- 8.5. RT Level Boundary Scan -- 8.5.1. Inserting Boundary Scan Test Hardware for CUT -- 8.5.2. Two Module Test Case -- 8.5.3. Virtual Boundary Scan Tester -- 8.6. Boundary Scan Description Language -- 8.7. Summary -- References -- 9. Logic Built-in Self-test -- 9.1. BIST Basics -- 9.1.1. Memory-based BIST -- 9.1.2. BIST Effectiveness -- 9.1.3. BISTTypes -- 9.1.4. Designing a BIST -- 9.2. Test Pattern Generation -- 9.2.1. Engaging TPGs -- 9.2.2. Exhaustive Counters -- 9.2.3. Ring Counters -- 9.2.4. Twisted Ring Counter -- 9.2.5. Linear Feedback Shift Register --

Note continued: 9.3. Output Response Analysis -- 9.3.1. Engaging ORAs -- 9.3.2. One's Counter -- 9.3.3. Transition Counter -- 9.3.4. Parity Checking -- 9.3.5. Serial LFSRs (SISR) -- 9.3.6. Parallel Signature Analysis -- 9.4. BIST Architectures -- 9.4.1. BTST-related Terminologies -- 9.4.2. Centralized and Separate Board-level BIST Architecture (CSBL) -- 9.4.3. Built-in Evaluation and Self-test (BEST) -- 9.4.4. Random Test Socket (RTS) -- 9.4.5. LSSD On-chip Self Test -- 9.4.6. Self-testing Using MTSR and SRSG -- 9.4.7. Concurrent BIST -- 9.4.8. BILBO -- 9.4.9. Enhancing Coverage -- 9.5. RT Level BIST Design -- 9.5.1. CUT Design, Simulation, and Synthesis -- 9.5.2. RTS BIST Insertion -- 9.5.3. Configuring the RTS BIST -- 9.5.4. Incorporating Configurations in BIST -- 9.5.5. Design of STUMPS -- 9.5.6. RTS and STUMPS Results -- 9.6. Summary -- References -- 10. Test Compression -- 10.1. Test Data Compression -- 10.2. Compression Methods -- 10.2.1. Code-based Schemes -- 10.2.2. Scan-based Schemes -- 10.3. Decompression Methods -- 10.3.1. Decompression Unit Architecture -- 10.3.2. Cyclical Scan Chain -- 10.3.3. Code-based Decompression -- 10.3.4. Scan-based Decompression -- 10.4. Summary -- References -- 11. Memory Testing by Means of Memory BIST -- 11.1. Memory Testing -- 11.2. Memory Structure -- 11.3. Memory Fault Model -- 11.3.1. Stuck-At Faults -- 11.3.2. Transition Faults -- 11.3.3. Coupling Faults -- 11.3.4. Bridging and State CFs -- 11.4. Functional Test Procedures -- 11.4.1. March Test Algorithms -- 11.4.2. March C-Algorithm -- 11.4.3. MATS+Algorithm -- 11.4.4. Other March Tests -- 11.5. MBIST Methods -- 11.5.1. Simple March MBIST -- 11.5.2. March C- MBIST -- 11.5.3. Disturb MBIST -- 11.6. Summary -- References

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