MARC details
000 -LEADER |
fixed length control field |
09127cam a2200409Ka 4500 |
001 - CONTROL NUMBER |
control field |
700167288 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
OCoLC |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20180421115108.0 |
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS--GENERAL INFORMATION |
fixed length control field |
m d |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr cn||||||||| |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
110203s2011 nyua ob 001 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781441975485 (electronic bk.) |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
1441975489 (electronic bk.) |
035 ## - SYSTEM CONTROL NUMBER |
System control number |
(OCoLC)700167288 |
Canceled/invalid control number |
(OCoLC)695849409 |
037 ## - SOURCE OF ACQUISITION |
Stock number |
978-1-4419-7547-8 |
Source of stock number/acquisition |
Springer |
Note |
http://www.springerlink.com |
040 ## - CATALOGING SOURCE |
Original cataloging agency |
GW5XE |
Language of cataloging |
eng |
Transcribing agency |
GW5XE |
Modifying agency |
OCLCQ |
-- |
QE2 |
-- |
MYPMP |
-- |
SNK |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
Classification number |
TK7874 |
Item number |
.N38 2011 |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.3815 |
Edition number |
22 |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Navabi, Zainalabedin |
245 10 - TITLE STATEMENT |
Title |
Digital system test and testable design |
Remainder of title |
using HDL models and architectures / |
Statement of responsibility, etc |
Zainalabedin Navabi |
250 ## - EDITION STATEMENT |
Edition statement |
1st ed. |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
Place of publication, distribution, etc |
New York : |
Name of publisher, distributor, etc |
Springer, |
Date of publication, distribution, etc |
c2011 |
300 ## - PHYSICAL DESCRIPTION |
Extent |
1 online resource (xxiii, 435 p.) : |
Other physical details |
ill |
504 ## - BIBLIOGRAPHY, ETC. NOTE |
Bibliography, etc |
Includes bibliographical references and index |
505 00 - FORMATTED CONTENTS NOTE |
Formatted contents note |
Note continued: |
Miscellaneous information |
2.8.3. |
Title |
Simple Sequential Testbench -- |
Miscellaneous information |
2.8.4. |
Title |
Limiting Data Sets -- |
Miscellaneous information |
2.8.5. |
Title |
Synchronized Data and Response Handling -- |
Miscellaneous information |
2.8.6. |
Title |
Random Time Intervals -- |
Miscellaneous information |
2.8.7. |
Title |
Text IO -- |
Miscellaneous information |
2.8.8. |
Title |
Simulation Code Coverage -- |
Miscellaneous information |
2.9. |
Title |
PLI Basics -- |
Miscellaneous information |
2.9.1. |
Title |
Access Routines -- |
Miscellaneous information |
2.9.2. |
Title |
Steps for HDL/PLI Implementation -- |
Miscellaneous information |
2.9.3. |
Title |
Fault Injection in the HDL/PLI Environment -- |
Miscellaneous information |
2.10. |
Title |
Summary -- |
-- |
References -- |
Miscellaneous information |
3. |
Title |
Fault and Defect Modeling -- |
Miscellaneous information |
3.1. |
Title |
Fault Modeling -- |
Miscellaneous information |
3.1.1. |
Title |
Fault Abstraction -- |
Miscellaneous information |
3.1.2. |
Title |
Functional Faults -- |
Miscellaneous information |
3.1.3. |
Title |
Structural Faults -- |
Miscellaneous information |
3.2. |
Title |
Structural Gate Level Faults -- |
Miscellaneous information |
3.2.1. |
Title |
Recognizing Faults -- |
Miscellaneous information |
3.2.2. |
Title |
Stuck-Open Faults -- |
Miscellaneous information |
3.2.3. |
Title |
Stuck-at-0 Faults -- |
Miscellaneous information |
3.2.4. |
Title |
Stuck-at-1 Faults -- |
Miscellaneous information |
3.2.5. |
Title |
Bridging Faults -- |
Miscellaneous information |
3.2.6. |
Title |
State-Dependent Faults -- |
Miscellaneous information |
3.2.7. |
Title |
Multiple Faults -- |
Miscellaneous information |
3.2.8. |
Title |
Single Stuck-at Structural Faults -- |
Miscellaneous information |
3.2.9. |
Title |
Detecting Single Stuck-at Faults -- |
Miscellaneous information |
3.3. |
Title |
Issues Related to Gate Level Faults -- |
Miscellaneous information |
3.3.1. |
Title |
Deteeting Bridging Faults -- |
Miscellaneous information |
3.3.2. |
Title |
Undetectable Faults -- |
Miscellaneous information |
3.3.3. |
Title |
Redundant Faults -- |
Miscellaneous information |
3.4. |
Title |
Fault Collapsing -- |
Miscellaneous information |
3.4.1. |
Title |
Indistinguishable Faults -- |
Miscellaneous information |
3.4.2. |
Title |
Equivalent Single Stuck-al Faults -- |
Miscellaneous information |
3.4.3. |
Title |
Gate-Oriented Fault Collapsing -- |
Miscellaneous information |
3.4.4. |
Title |
Line-Oriented Fault Collapsing -- |
Miscellaneous information |
3.4.5. |
Title |
Problem with Reconvergenl Fanouts -- |
Miscellaneous information |
3.4.6. |
Title |
Dominance Fault Collapsing -- |
Miscellaneous information |
3.5. |
Title |
Fault Collapsing in Verilog -- |
Miscellaneous information |
3.5.1. |
Title |
Verilog Testbench for Fault Collapsing -- |
Miscellaneous information |
3.5.2. |
Title |
PLI Implementation of Fault Collapsing -- |
Miscellaneous information |
3.6. |
Title |
Summary -- |
-- |
References -- |
Miscellaneous information |
4. |
Title |
Fault Simulation Applications and Methods -- |
Miscellaneous information |
4.1. |
Title |
Fault Simulation -- |
Miscellaneous information |
4.1.1. |
Title |
Gate-Level Fault Simulation -- |
Miscellaneous information |
4.1.2. |
Title |
Fault Simulation Requirements -- |
Miscellaneous information |
4.1.3. |
Title |
HDL Environment -- |
Miscellaneous information |
4.1.4. |
Title |
Sequential Circuit Fault Simulation -- |
Miscellaneous information |
4.1.5. |
Title |
Fault Dropping -- |
Miscellaneous information |
4.1.6. |
Title |
Related Terminologies -- |
Miscellaneous information |
4.2. |
Title |
Fault Simulation Applications -- |
Miscellaneous information |
4.2.1. |
Title |
Fault Coverage -- |
Miscellaneous information |
4.2.2. |
Title |
Fault Simulation in Test Generation -- |
505 00 - FORMATTED CONTENTS NOTE |
Formatted contents note |
Note continued: |
Miscellaneous information |
4.2.3. |
Title |
Fault Dictionary Creation -- |
Miscellaneous information |
4.3. |
Title |
Fault Simulation Technologies -- |
Miscellaneous information |
4.3.1. |
Title |
Serial Fault Simulation -- |
Miscellaneous information |
4.3.2. |
Title |
Parallel Fault Simulation -- |
Miscellaneous information |
4.3.3. |
Title |
Concurrent Fault Simulation -- |
Miscellaneous information |
4.3.4. |
Title |
Deductive Fault Simulation -- |
Miscellaneous information |
4.3.5. |
Title |
Comparison of Deductive Fault Simulation -- |
Miscellaneous information |
4.3.6. |
Title |
Critical Path Tracing Fault Simulation -- |
Miscellaneous information |
4.3.7. |
Title |
Differential Fault Simulation -- |
Miscellaneous information |
4.4. |
Title |
Summary -- |
-- |
References -- |
Miscellaneous information |
5. |
Title |
Test Pattern Generation Methods and Algorithms -- |
Miscellaneous information |
5.1. |
Title |
Test Generation Basics -- |
Miscellaneous information |
5.1.1. |
Title |
Boolean Difference -- |
Miscellaneous information |
5.1.2. |
Title |
Test Generation Process -- |
Miscellaneous information |
5.1.3. |
Title |
Fault and Tests -- |
Miscellaneous information |
5.1.4. |
Title |
Terminologies and Definitions -- |
Miscellaneous information |
5.2. |
Title |
Controllability and Observability -- |
Miscellaneous information |
5.2.1. |
Title |
Controllability -- |
Miscellaneous information |
5.2.2. |
Title |
Observability -- |
Miscellaneous information |
5.2.3. |
Title |
Probability-Based Controllability and Observability -- |
Miscellaneous information |
5.2.4. |
Title |
SCOAP Controllability and Observability -- |
Miscellaneous information |
5.2.5. |
Title |
Distances Based -- |
Miscellaneous information |
5.3. |
Title |
Random Test Generation -- |
Miscellaneous information |
5.3.1. |
Title |
Limiting Number of Random Tests -- |
Miscellaneous information |
5.3.2. |
Title |
Combinational Circuit RTG -- |
Miscellaneous information |
5.3.3. |
Title |
Sequential Circuit RTG -- |
Miscellaneous information |
5.4. |
Title |
Summary -- |
-- |
References -- |
Miscellaneous information |
6. |
Title |
Deterministic Test Generation Algorithms -- |
Miscellaneous information |
6.1. |
Title |
Deterministic Test Generation Methods -- |
Miscellaneous information |
6.1.1. |
Title |
Two-Phase Test Generation -- |
Miscellaneous information |
6.1.2. |
Title |
Fault-Oriented TG Basics -- |
Miscellaneous information |
6.1.3. |
Title |
D-Algorithm -- |
Miscellaneous information |
6.1.4. |
Title |
PODEM (Path-Oriented Test Generation) -- |
Miscellaneous information |
6.1.5. |
Title |
Other Deterministic Fault-Oriented TG Methods -- |
Miscellaneous information |
6.1.6. |
Title |
Fault-Independent Test Generation -- |
Miscellaneous information |
6.2. |
Title |
Sequential Circuit Test Generation -- |
Miscellaneous information |
6.3. |
Title |
Test Data Compaction -- |
Miscellaneous information |
6.3.1. |
Title |
Forms of Test Compaction -- |
Miscellaneous information |
6.3.2. |
Title |
Test Compatibility -- |
Miscellaneous information |
6.3.3. |
Title |
Static Compaction -- |
Miscellaneous information |
6.3.4. |
Title |
Dynamic Compaction -- |
Miscellaneous information |
6.4. |
Title |
Summary -- |
-- |
References -- |
Miscellaneous information |
7. |
Title |
Design for Test by Means of Scan -- |
Miscellaneous information |
7.1. |
Title |
Making Circuits Testable -- |
Miscellaneous information |
7.1.1. |
Title |
Tradeoffs -- |
Miscellaneous information |
7.1.2. |
Title |
Testing Sequential Circuits -- |
Miscellaneous information |
7.1.3. |
Title |
Testability of Combinational Circuits -- |
Miscellaneous information |
7.2. |
Title |
Testability Insertion -- |
Miscellaneous information |
7.2.1. |
Title |
Improving Observability -- |
505 00 - FORMATTED CONTENTS NOTE |
Formatted contents note |
Note continued: |
Miscellaneous information |
7.2.2. |
Title |
Improving Controllability -- |
Miscellaneous information |
7.2.3. |
Title |
Sharing Observability Pins -- |
Miscellaneous information |
7.2.4. |
Title |
Sharing Control Pins -- |
Miscellaneous information |
7.2.5. |
Title |
Reducing Select Inputs -- |
Miscellaneous information |
7.2.6. |
Title |
Simultaneous Control and Observation -- |
Miscellaneous information |
7.3. |
Title |
Full Scan DFTTechnique -- |
Miscellaneous information |
7.3.1. |
Title |
Full Scan Insertion -- |
Miscellaneous information |
7.3.2. |
Title |
Flip-Flop Structures -- |
Miscellaneous information |
7.3.3. |
Title |
Full Scan Design and Test -- |
Miscellaneous information |
7.4. |
Title |
Scan Architectures -- |
Miscellaneous information |
7.4.1. |
Title |
Full Scan Design -- |
Miscellaneous information |
7.4.2. |
Title |
Shadow Register DFT -- |
Miscellaneous information |
7.4.3. |
Title |
Partial Scan Methods -- |
Miscellaneous information |
7.4.4. |
Title |
Multiple Scan Design -- |
Miscellaneous information |
7.4.5. |
Title |
Other Scan Designs -- |
Miscellaneous information |
7.5. |
Title |
RT Level Scan Design -- |
Miscellaneous information |
7.5.1. |
Title |
RTL Design Full Scan -- |
Miscellaneous information |
7.5.2. |
Title |
RTL Design Multiple Scan -- |
Miscellaneous information |
7.5.3. |
Title |
Scan Designs for RTL -- |
Miscellaneous information |
7.6. |
Title |
Summary -- |
-- |
References -- |
Miscellaneous information |
8. |
Title |
Standard IEEE Test Access Methods -- |
Miscellaneous information |
8.1. |
Title |
Boundary Scan Basics -- |
Miscellaneous information |
8.2. |
Title |
Boundary Scan Architecture -- |
Miscellaneous information |
8.2.1. |
Title |
Test Access Port -- |
Miscellaneous information |
8.2.2. |
Title |
Boundary Scan Registers -- |
Miscellaneous information |
8.2.3. |
Title |
TAP Controller -- |
Miscellaneous information |
8.2.4. |
Title |
Decoder Unit -- |
Miscellaneous information |
8.2.5. |
Title |
Select and Other Units -- |
Miscellaneous information |
8.3. |
Title |
Boundary Scan Test Instructions -- |
Miscellaneous information |
8.3.1. |
Title |
Mandatory Instructions -- |
Miscellaneous information |
8.4. |
Title |
Board Level Scan Chain Structure -- |
Miscellaneous information |
8.4.1. |
Title |
One Serial Scan Chain -- |
Miscellaneous information |
8.4.2. |
Title |
Multiple-Scan Chain with One Control Test Port -- |
Miscellaneous information |
8.4.3. |
Title |
Multiple-Scan Chains with One TDI, TDO but Multiple TMS -- |
Miscellaneous information |
8.4.4. |
Title |
Multiple-Scan Chain, Multiple Access Port -- |
Miscellaneous information |
8.5. |
Title |
RT Level Boundary Scan -- |
Miscellaneous information |
8.5.1. |
Title |
Inserting Boundary Scan Test Hardware for CUT -- |
Miscellaneous information |
8.5.2. |
Title |
Two Module Test Case -- |
Miscellaneous information |
8.5.3. |
Title |
Virtual Boundary Scan Tester -- |
Miscellaneous information |
8.6. |
Title |
Boundary Scan Description Language -- |
Miscellaneous information |
8.7. |
Title |
Summary -- |
-- |
References -- |
Miscellaneous information |
9. |
Title |
Logic Built-in Self-test -- |
Miscellaneous information |
9.1. |
Title |
BIST Basics -- |
Miscellaneous information |
9.1.1. |
Title |
Memory-based BIST -- |
Miscellaneous information |
9.1.2. |
Title |
BIST Effectiveness -- |
Miscellaneous information |
9.1.3. |
Title |
BISTTypes -- |
Miscellaneous information |
9.1.4. |
Title |
Designing a BIST -- |
Miscellaneous information |
9.2. |
Title |
Test Pattern Generation -- |
Miscellaneous information |
9.2.1. |
Title |
Engaging TPGs -- |
Miscellaneous information |
9.2.2. |
Title |
Exhaustive Counters -- |
Miscellaneous information |
9.2.3. |
Title |
Ring Counters -- |
Miscellaneous information |
9.2.4. |
Title |
Twisted Ring Counter -- |
Miscellaneous information |
9.2.5. |
Title |
Linear Feedback Shift Register -- |
505 00 - FORMATTED CONTENTS NOTE |
Formatted contents note |
Note continued: |
Miscellaneous information |
9.3. |
Title |
Output Response Analysis -- |
Miscellaneous information |
9.3.1. |
Title |
Engaging ORAs -- |
Miscellaneous information |
9.3.2. |
Title |
One's Counter -- |
Miscellaneous information |
9.3.3. |
Title |
Transition Counter -- |
Miscellaneous information |
9.3.4. |
Title |
Parity Checking -- |
Miscellaneous information |
9.3.5. |
Title |
Serial LFSRs (SISR) -- |
Miscellaneous information |
9.3.6. |
Title |
Parallel Signature Analysis -- |
Miscellaneous information |
9.4. |
Title |
BIST Architectures -- |
Miscellaneous information |
9.4.1. |
Title |
BTST-related Terminologies -- |
Miscellaneous information |
9.4.2. |
Title |
Centralized and Separate Board-level BIST Architecture (CSBL) -- |
Miscellaneous information |
9.4.3. |
Title |
Built-in Evaluation and Self-test (BEST) -- |
Miscellaneous information |
9.4.4. |
Title |
Random Test Socket (RTS) -- |
Miscellaneous information |
9.4.5. |
Title |
LSSD On-chip Self Test -- |
Miscellaneous information |
9.4.6. |
Title |
Self-testing Using MTSR and SRSG -- |
Miscellaneous information |
9.4.7. |
Title |
Concurrent BIST -- |
Miscellaneous information |
9.4.8. |
Title |
BILBO -- |
Miscellaneous information |
9.4.9. |
Title |
Enhancing Coverage -- |
Miscellaneous information |
9.5. |
Title |
RT Level BIST Design -- |
Miscellaneous information |
9.5.1. |
Title |
CUT Design, Simulation, and Synthesis -- |
Miscellaneous information |
9.5.2. |
Title |
RTS BIST Insertion -- |
Miscellaneous information |
9.5.3. |
Title |
Configuring the RTS BIST -- |
Miscellaneous information |
9.5.4. |
Title |
Incorporating Configurations in BIST -- |
Miscellaneous information |
9.5.5. |
Title |
Design of STUMPS -- |
Miscellaneous information |
9.5.6. |
Title |
RTS and STUMPS Results -- |
Miscellaneous information |
9.6. |
Title |
Summary -- |
-- |
References -- |
Miscellaneous information |
10. |
Title |
Test Compression -- |
Miscellaneous information |
10.1. |
Title |
Test Data Compression -- |
Miscellaneous information |
10.2. |
Title |
Compression Methods -- |
Miscellaneous information |
10.2.1. |
Title |
Code-based Schemes -- |
Miscellaneous information |
10.2.2. |
Title |
Scan-based Schemes -- |
Miscellaneous information |
10.3. |
Title |
Decompression Methods -- |
Miscellaneous information |
10.3.1. |
Title |
Decompression Unit Architecture -- |
Miscellaneous information |
10.3.2. |
Title |
Cyclical Scan Chain -- |
Miscellaneous information |
10.3.3. |
Title |
Code-based Decompression -- |
Miscellaneous information |
10.3.4. |
Title |
Scan-based Decompression -- |
Miscellaneous information |
10.4. |
Title |
Summary -- |
-- |
References -- |
Miscellaneous information |
11. |
Title |
Memory Testing by Means of Memory BIST -- |
Miscellaneous information |
11.1. |
Title |
Memory Testing -- |
Miscellaneous information |
11.2. |
Title |
Memory Structure -- |
Miscellaneous information |
11.3. |
Title |
Memory Fault Model -- |
Miscellaneous information |
11.3.1. |
Title |
Stuck-At Faults -- |
Miscellaneous information |
11.3.2. |
Title |
Transition Faults -- |
Miscellaneous information |
11.3.3. |
Title |
Coupling Faults -- |
Miscellaneous information |
11.3.4. |
Title |
Bridging and State CFs -- |
Miscellaneous information |
11.4. |
Title |
Functional Test Procedures -- |
Miscellaneous information |
11.4.1. |
Title |
March Test Algorithms -- |
Miscellaneous information |
11.4.2. |
Title |
March C-Algorithm -- |
Miscellaneous information |
11.4.3. |
Title |
MATS+Algorithm -- |
Miscellaneous information |
11.4.4. |
Title |
Other March Tests -- |
Miscellaneous information |
11.5. |
Title |
MBIST Methods -- |
Miscellaneous information |
11.5.1. |
Title |
Simple March MBIST -- |
Miscellaneous information |
11.5.2. |
Title |
March C- MBIST -- |
Miscellaneous information |
11.5.3. |
Title |
Disturb MBIST -- |
Miscellaneous information |
11.6. |
Title |
Summary -- |
-- |
References |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Digital integrated circuits |
General subdivision |
Testing |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Digital integrated circuits |
General subdivision |
Design and construction |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Verilog (Computer hardware description language) |
655 #4 - INDEX TERM--GENRE/FORM |
Genre/form data or focus term |
Electronic books |
773 0# - HOST ITEM ENTRY |
Title |
SpringerLink |
Record control number |
(OCoLC)43927870 |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
<a href="http://dx.doi.org/10.1007/978-1-4419-7548-5">http://dx.doi.org/10.1007/978-1-4419-7548-5</a> |
Materials specified |
SpringerLINK |
Public note |
Connect to electronic resource |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
<a href="http://proxy.ohiolink.edu:9099/login?url=http://dx.doi.org/10.1007/978-1-4419-7548-5">http://proxy.ohiolink.edu:9099/login?url=http://dx.doi.org/10.1007/978-1-4419-7548-5</a> |
Materials specified |
SpringerLINK |
Public note |
Connect to electronic resource (off-campus access) |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
Dewey Decimal Classification |
Item type |
Books |