TY  - BOOK
AU  - Pedroni,Volnei A.
TI  - Digital electronics and design with VHDL
SN  - 9780123742704 (pbk. : alk. paper)
AV  - TK7885.7 .P44 2008
U1  - 621.39/2 22
PY  - 2008///
CY  - Amsterdam
PB  - Boston, Elsevier Morgan Kaufmann Publishers
KW  - VHDL (Computer hardware description language)
KW  - Digital integrated circuits
KW  - Design and construction
KW  - Data processing
N1  - Includes bibliographical references (p. 673-677) and index; Contents 
Preface
List of enumerated examples and exercises
1 Introduction
1.1 Historical notes
1.2 Analog versus digital
1.3 Bits, bytes, and words
1.4 Digital circuits
1.5 Combinational circuits versus sequential circuits 
1.6 Integrated circuits (ICs)
1.7 Printed circuit board (PCB)
1.8 Logic values versus physical values
1.9 Non-programmable, programmable, and hardware-programmable
1.10 Binary waveforms
1.11 DC, AC, and transient responses
1.12 Programmable logic devices (PLDs)
1.13 Circuit synthesis and simulation with VHDL
1.14 Circuit simulation with Spice
1.15 Gate-level versus transistor-level analysis
2 Binary representations
2.1 Binary code
2.2 Octal and hexadecimal codes
2.3 Gray code
2.4 BCD code
2.5 Codes for negative numbers
2.6 Floating-point representation
2.7 ASCII code
2.8 Unicode
2.9 Exercises
3 Binary arithmetic
3.1 Unsigned addition
3.2 Signed addition and subtraction
3.3 Shift operations
3.4 Unsigned multiplication
3.5 Signed multiplication
3.6 Unsigned division
3.7 Signed division
3.8 Floating-point addition and subtraction
3.9 Floating-point multiplication
3.10 Floating-point division
3.11 Exercises
4 Introduction to digital circuits
4.1 Introduction to MOS transistors
4.2 Inverter and CMOS logic
4.3 AND and NAND gates
4.4 OR and NOR gates
4.5 XOR and XNOR gates
4.6 Modulo-2 adder
4.7 Buffer
4.8 Tri-state buffer
4.9 Open-drain buffer
4.10 D-type flip-flop
4.11 Shift register
4.12 Counters
4.13 Pseudo-random sequence generator
4.14 Exercises
5.1 Boolean algebra
5.2 Truth tables
5.3 Minterms and SOP equations
5.4 Maxterms and POS equations
5.5 Standard circuits for SOP and POS equations
5.6 Karnaugh maps
5.7 Large Karnaugh maps
5.8 Other function-simplification techniques
5.9 Propagation delay and glitches
5.10 Exercises
6 Line codes 
6.1 The use of line codes
6.2 Parameters and types of line codes
6.3 Unipolar codes
6.4 Polar codes
6.5 Bipolar codes
6.6 Biphase/Manchester codes
6.7 MLT codes
6.8 mB/nB codes
6.9 PAM codes
6.10 Exercises
7 Error-detecting/correcting codes 
7.1 Introduction
7.2 Single-parity-check (SPC) codes
7.3 Cyclic redundancy check (CRC) codes
7.4 Hamming codes
7.5 Reed Solomon codes
7.6 Convolutional codes and Viterbi decoder
7.7 Turbo codes
7.8 Low-density parity-check (LDPC) codes
7.9 Exercises
8 Bipolar junction transistor (BJT)
8.1 Semiconductors
8.2 The bipolar junction transistor (BJT)
8.3 I-V characteristics
8.4 DC response
8.5 Transient response
8.6 AC response
8.7 Modern BJTs
8.8 Exercises
9 MOS transistor
9.1 Semiconductors 
9.2 The field-effect transistor (MOSFET)
9.3 I-V characteristics
9.4 DC response
9.5 CMOS inverter
9.6 Transient response
9.7 AC response
9.8 Modern MOSFETs
9.9 Exercises
10 Logic families and I/Os Logic architectures and I/Os
10.1 BJT-based logic families
10.2 Diode-transistor logic (DTL)
10.3 Transistor-transistor logic (TTL)
10.4 Emitter-coupled logic (ECL)
10.5 MOS-based logic families
10.6 CMOS logic
10.7 Other static MOS architectures
10.8 Dynamic MOS architectures
10.9 Modern I/O standards
10.10 Exercises
11 Combinational logic circuits
11.1 Combinational versus sequential logic
11.2 Logical versus arithmetic circuits
11.3 Fundamental logic gates 
11.4 Compound gates
11.5 Encoders and decoders
11.6 Multiplexer
11.7 Parity detector
11.8 Priority encoder
11.9 Binary sorter
11.10 Barrel shifters
11.11 Non-overlapping clock generators
11.12 Short-pulse generators
11.13 Schmitt triggers
11.14 Memories
11.15 Exercises
11.16 Exercises with VHDL
11.17 Exercises with SPICE
12 Combinational arithmetic circuits
12.1 Arithmetic versus logical functions
12.2 Basic adders
12.3 Fast adders
12.4 Bit-serial adder
12.5 Signed adders/subtracters
12.6 Incrementer, decrementer, and two¿s complementer
12.7 Comparators
12.8 ALU (arithmetic-logic unit)
12.9 Multipliers
12.10 Dividers
12.11 Exercises
12.12 Exercises with VHDL
12.13 Exercises with SPICE
13 Registers
13.1 Sequential versus combinational logic
13.2 SR latch (SRL)
13.3 D latch (DL)
13.4 D flip-flop (DFF)
13.5 Master-slave DFFs
13.6 Pulse-based DFFs
13.7 Dual-edge DFFs
13.8 Statistically low-power DFFs
13.9 DFF control ports
13.10 T flip-flop (TFF)
13.11 Exercises
13.12 Exercises with SPICE
14 Sequential circuits
14.1 Shift registers
14.2 Synchronous counters
14.3 Asynchronous counters
14.4 Signal generators 
14.5 Frequency dividers
14.6 PLL and prescalers
14.7 Pseudo-random sequence generators
14.8 Scramblers and descramblers
14.9 Exercises
14.10 Exercises with VHDL
14.11 Exercises with SPICE
15 Finite state machines
15.1 FSM model
15.2 Design of finite state machines
15.3 System resolution and glitches
15.4 Design of large FSMs
15.5 Design of FSMs with complex combinational logic
15.6 Design of symmetric-phase frequency dividers
15.7 FSM encoding styles
15.8 Exercises
15.9 Exercises with VHDL
16 Volatile memories
16.1 Memory types
16.2 SRAM (Static Random Access Memory)
16.3 Dual and Quad Data Rate SRAMs (DDR and QDR)
16.4 DRAM (Dynamic Random Access Memory)
16.5 SDRAM (Synchronous DRAM)
16.6 Dual Data Rate SDRAMs (DDR, DDR2, and DDR3)
16.7 CAM (Content-Addressable Memory) for Cache Memories
16.8 Exercises
17 Non-volatile memories
17.1 Memory types
17.2 MP-ROM (Mask-Programmed ROM)
17.3 OTP ROM (One-Time Programmable ROM or PROM)
17.4 EPROM (Electrically Programmable ROM)
17.5 EEPROM (Electrically Erasable-Programmable ROM)
17.6 Flash memory
17.7 Next generation memories: FRAM, MRAM, PRAM
17.8 Exercises
18 Programmable logic devices (PLDs)
18.1 The concept of programmable logic devices
18.2 SPLDs
18.3 CPLDs
18.4 FPGAs
18.5 Exercises
19 VHDL summary
19.1 About VHDL 
19.2 Code structure
19.3 Fundamental VHDL packages 
19.4 Pre-defined data types
19.5 User-defined data types
19.6 Operators
19.7 Attributes
19.8 Concurrent versus sequential code
19.9 Concurrent code (WHEN, GENERATE)
19.10 Sequential code (IF, CASE, LOOP, WAIT)
19.11 Objects (CONSTANT, SIGNAL, VARIABLE)
19.12 Packages
19.13 Components
19.14 Functions
19.15 Procedures
19.16 VHDL template for FSMs
19.17 Exercises
20 VHDL design of combinational logic circuits
20.1: Generic address decoder
20.2: BCD-to-SSD conversion function
20.3: Generic multiplexer
20.4: Generic priority encoder
20.5: Design of ROM memory
20.6 Design of Synchronous RAM Memories
20.7 Exercises
	
21 VHDL design of combinational arithmetic circuits
21.1 Carry-ripple adder
21.2 Carry-lookahead adder
21.3 Signed and unsigned adders / subtracters
21.4 Signed and unsigned multipliers / dividers 
21.5 ALU
21.6 Exercises 
22 VHDL design of regular sequential circuits 
22.1 Shift register with load
22.2 Switch debouncer
22.3 Timer
22.4 Fibonacci series generator
22.5 Frequency meters
22.6 Neural networks
22.7 Exercises 
23 VHDL design of state machines
23.1 String detector
23.2 ¿Universal¿ signal generator
23.3 Car alarm
23.4 LCD driver
23.5 Exercises 
24 Simulation with VHDL testbenches
24.1 Synthesis versus simulation
24.2 Stimulus generation
24.3 Writing testbenches ¿ part 1
24.4 Writing testbenches ¿ part 2
24.5 Functional simulations
24.6 Timing simulations
24.7 Exercises
25 Simulation with SPICE
25.1 About SPICE
25.2 Types of analysis
25.3 Basic structure of SPICE code
25.4 Declarations of electronic devices
25.5 Declarations of independent DC sources
25.6 Declarations of independent AC sources
25.7 Declarations of dependent sources
25.8 SPICE inputs and outputs
25.9 DC response examples
25.10 Transient response examples
25.11 AC response example
25.12 Subcircuits
25.13 Exercises involving combinational logic circuits
25.14 Exercises involving combinational arithmetic circuits
25.15 Exercises involving registers
25.16 Exercises involving sequential circuits
Appendices
A ModelSim Tutorial
B PSpice Tutorial
References 
Index
ER  -